FPGAs are not designed to have high clock speeds. They are designed to rely on synchronous logic, and they rely on timing closure to run well. If you have an FPGA that is large and complex, and that runs at a high frequency, then you may struggle to get it running efficiently and to achieve timing closure. There are a few things that you can do to get the best out of your FPGA. These tips and best practices will help to keep a high-performance FPGA running optimally even with large programs.
Synchronous Techniques Make Sense
The place and route tools that you see these days are based on static timing analysis and are intended to be used where synchronous logic is applied. If you try to use them with a self-clocking circuit or an asynchronous state machine, then you can expect to see some quirky performance. Try to make sure that all of the registers in a clock domain are clocked from the same clock. That may sound obvious if you’re used to working with smaller FPGAs, but with bigger boards that have multiple clocks and registers it gets harder to do.
All registers in an FPGA will have a clock enable. Use it and use a single clock within each domain. The clock enable should be used in preference to have a locally generated clock. Use pipeline stages to ensure that there are as few delays as possible in the path. It’s inevitable that there will be some delays, but your goal should be to keep the delays small. In addition, use register balancing to speed up any other paths nearby, and to break up any routing delays so they are spread across the chip.
Timing Problems Can Be Tackled
Timing problems are something that every FPGA developer is going to run into eventually. There are a lot of things that you can do to fix the issue, but there’s an order that you should approach the problem to make sure that you’re not wasting effort and resources. Often, the problems can be fixed in the development process simply by adding a pipeline stage.
If a pipeline stage isn’t enough, because the problematic timing path has several cycles to execute, then you can use multicycle constraints to ensure that it sticks to the required timing. Sometimes, you may want to combine strategies change the logic to allow for multiple cycles for the path, and then use constraints to avoid violations.
Understand the Underlying Logic
When you’re writing HDL code, try to understand exactly what it will do. It can help to try breaking down small snippets of code, so that you use the best HDL for the circumstances. This is one area where people who have experience with other software coding languages may actually struggle. With high level languages it is easy to get sloppy, and to write a CASE statement where an IF/ELSIF would work better.
With FPGAs, you should use a CASE statement if you want a decoder and use an IF/ELSIF construct if you are after a priority encoder. Understanding how the code will be executed, step by step, will help you to pick the most efficient way of writing it. This is something that all coders can benefit from. Have you ever, in a desktop language, struggled with debugging only to fall trap to the difference between DO… WHILE versus WHILE?
The I/O Ring Offers Better Timing
Whenever possible, you should use the registers that are in the I/O ring. These will offer guaranteed input/output timing and may help to save resources too.
Learn Your Device
Each FPGA has its own specifications and architecture, and if you can keep track of the logic units and the lookup tables, then you’ll have far fewer headaches. Try to take advantage of any specific features that the target architecture has such as hardware multipliers or DLLs. They exist to make your job easier, and if you’re not using them then you’re spending a fortune on a board that is over-specked for the job that it is doing.
More Ways To Improve Timing
One common problem is overloaded nets. You can help to solve this by using duplication either manually or using your tools. If you go the manual route, then you may need to tell the tools to not eliminate any redundant logic. This is a case of the tools trying to be helpful but not understanding the purpose of the code. Automatic duplication is a desirable side-effect if you decrease the maximum fanout limit.
If this doesn’t work, then you can prioritize the net that is failing. Again, in some cases this is something that you can do with tools. In other cases, you’ll need to get smart and work around the limitations. Set a constraint that is very slightly faster than the target frequency, and with luck the tools will route that constrained net before others.
Don’t Reinvent The Wheel
Often, FPGA vendor core generators will come with pre-done accumulators, comparators and other features. These are already highly optimized so can be a good option if you want to make sure that you are getting the best possible performance for particularly difficult functions.
Of course, on the flipside, if you have a highly specialist and confusing function, then you might want to write something to handle it yourself, and then replace the core that was shipped by the vendor. Your core may run faster or be heavily optimized for the one specific job that you want it to do.
Direct Components Inc fpga on sale are not quite the same as standard desktop computers, and if you’re new to this kind of programming then you may want to take some time to re-learn your approach to programming. It will take time to master, but the result will be very good for the standard of code that you write and will get you thinking about the logic on a much more careful level than you might have in the past.